Freescale Semiconductor /MK70F12 /MCG /C5

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Interpret as C5

7 43 0 0 00 0 0 0 0 0 0 0 0 (0)PRDIV0 0 (0)PLLSTEN0 0 (0)PLLCLKEN0 0 (0)PLLREFSEL0

PLLSTEN0=0, PLLCLKEN0=0, PLLREFSEL0=0, PRDIV0=0

Description

MCG Control 5 Register

Fields

PRDIV0

PLL0 External Reference Divider

0 (0): Divide Factor is 1

1 (1): Divide Factor is 2

2 (2): Divide Factor is 3

3 (3): Divide Factor is 4

4 (4): Divide Factor is 5

5 (5): Divide Factor is 6

6 (6): Divide Factor is 7

7 (7): Divide Factor is 8

PLLSTEN0

PLL0 Stop Enable

0 (0): MCGPLL0CLK and MCGPLL0CLK2X are disabled in any of the Stop modes.

1 (1): MCGPLL0CLK and MCGPLL0CLK2X are enabled if system is in Normal Stop mode.

PLLCLKEN0

PLL Clock Enable

0 (0): MCGPLL0CLK and MCGPLL0CLK2X are inactive.

1 (1): MCGPLL0CLK and MCGPLL0CLK2X are active.

PLLREFSEL0

PLL0 External Reference Select

0 (0): Selects OSC0 clock source as its external reference clock.

1 (1): Selects OSC1 clock source as its external reference clock.

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